1. Field of the Invention
This invention generally relates to adaptive sampling for semiconductor inspection recipe creation, defect review, and metrology.
2. Description of the Related Art
The following description and examples are not admitted to be prior art by virtue of their inclusion in this section.
Semiconductor manufacturing involves a large and complex set of imaging, etching, deposition, and planarization processes in order to construct sub-micron (down to a few tens of nanometers) geometrical patterns on a silicon substrate. The usual method for detecting most random and low probability systematic defects is to compare identical locations on adjacent dies on the wafer using imaging or scattering optical tool such as the KLA-Tencor 2900 Series or KLA-Tencor 9800 Series systems. However, this task is becoming more challenging as the process windows of tolerance become tighter. Tool noise (such as sensor noise and image misalignment due to image jitter and other sources) coupled with small variations in the wafer processing introduce noise in the difference measurements when comparing nominally identical locations in adjacent dies.
The design layout of the die is often used to identify critical regions (such as areas of high geometry density) and other so-called “hot spots” where defects can manifest themselves. By separating critical from non-critical regions, a more sensitive inspection can be performed in the critical areas and a less sensitive inspection in the less critical areas. U.S. Pat. No. 7,676,077 issued on Mar. 9, 2010 to Kulkarni et al., which is incorporated by reference as if fully set forth herein, describes this approach. However, in many circumstances, the design information may not be readily available.
Accordingly, it would be advantageous to develop methods and/or systems for wafer inspection-related applications that do not have one or more of the disadvantages described above.